Landing pad in interconnect and memory stacks: structure and formation of the same

ABSTRACT

A conductive landing pad structure is formed utilizing a selective deposition process on a surface of an electrically conductive structure that is embedded in a first dielectric material layer. The conductive landing pad structure is located on an entirety of a surface of the electrically conductive structure and does not extend onto the first dielectric material layer. A conductive metal-containing structure is formed on a physically exposed surface of the conductive landing pad structure. During the formation of the conductive metal-containing structure which includes ion beam etching and/or a wet chemical etch, no conductive landing pad material particles re-deposit on the sidewalls of the conductive metal-containing structure.

BACKGROUND

The present application relates to a semiconductor structure and amethod of forming the same. More particularly, the present applicationrelates to a semiconductor structure including a conductivemetal-containing structure that is located on a physically exposedsurface of a conductive landing pad structure and is devoid of anyre-deposited conductive landing pad material particles on the sidewallsthereof.

In interconnect device processing or memory device processing, aconductive landing pad and a conductive metal-containing material areformed as blanket layers on a dielectric material that includes anelectrically conductive structure. The blanket layers of the conductivelanding pad and the conductive metal-containing material are thenpatterned utilizing an ion beam and/or chemical wet etching process.During the etching process, conductive landing pad material isre-deposited as conductive landing pad material particles on thesidewalls of the patterned conductive metal-containing material. Thepresence of the conductive landing pad material particles degrades theyield of the resultant structure and can lead to unwanted shorts.

There is thus a need for providing a semiconductor structure in which nore-deposition of the conductive landing pad material occurs during thepatterning of a blanket layer of a conductive metal-containing material.

SUMMARY

A conductive landing pad structure is formed utilizing a selectivedeposition process on a surface of an electrically conductive structurethat is embedded in a first dielectric material layer. The conductivelanding pad structure is located on an entirety of a surface of theelectrically conductive structure and does not extend onto the firstdielectric material layer. A conductive metal-containing structure isformed on a physically exposed surface of the conductive landing padstructure. During the formation of the conductive metal-containingstructure which includes ion beam etching and/or a wet chemical etch, noconductive landing pad material particles re-deposit on the sidewalls ofthe conductive metal-containing structure. Thus, the resultant structuredoes not exhibit any shorts that are caused by the re-deposition of theconductive landing pad material on a sidewall of the conductivemetal-containing structure. Also, yield degradation has been mitigated.

In one aspect of the present application, a method of forming asemiconductor structure is provided. In one embodiment, the methodincludes forming, by selective deposition, a conductive landing padstructure on a physically exposed surface of an electrically conductivestructure that is embedded in a first dielectric material layer. Aconductive metal-containing material is then formed on the conductivelanding pad structure and a physically exposed portion of the firstdielectric material layer. Next, the conductive metal-containingmaterial is patterned to provide a conductive metal-containingstructure, wherein during the patterning no conductive landing padmaterial particles re-deposit on sidewalls of the metal-containingconductive structure.

In another aspect of the present application, a semiconductor structureis provided. In one embodiment, the semiconductor structure includes anelectrically conductive structure embedded in a first dielectricmaterial layer. A conductive landing pad structure is located on anentirety of a surface of the electrically conductive structure, aconductive metal-containing structure is located on an entirety of asurface of the conductive landing pad structure, and a contact structurephysically contacts at least one surface of the conductivemetal-containing structure. In accordance with the present application,the conductive landing pad structure, the conductive metal-containingstructure, and the contact structure are embedded in a second dielectricmaterial layer that is present above the first dielectric materiallayer, and the conductive metal-containing structure has sidewalls thatare devoid of re-deposited conductive landing pad material particles.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of an exemplary semiconductor structureof the present application and during an early stage of fabrication, thestructure including a first dielectric material layer located on asurface of a substrate.

FIG. 2 is a cross sectional view of the exemplary semiconductorstructure of FIG. 1 after forming an opening into the first dielectricmaterial layer.

FIG. 3 is a cross sectional view of the exemplary semiconductorstructure of FIG. 2 after forming an electrically conductive structurein the opening.

FIG. 4 is a cross sectional view of the exemplary semiconductorstructure of FIG. 3 after forming, by selective deposition, a conductivelanding pad on a physically exposed surface of the electricallyconductive structure.

FIGS. 5A-5B are cross sectional views of the exemplary semiconductorstructure of FIG. 4 after performing a planarization process.

FIG. 6 is a cross sectional view of the exemplary semiconductorstructure of FIG. 5B after forming a conductive metal-containingmaterial.

FIG. 7 is a cross sectional view of the exemplary semiconductorstructure of FIG. 6 after forming a metal hard mask on the conductivemetal-containing material.

FIG. 8 is a cross sectional view of the exemplary semiconductorstructure of FIG. 7 after forming a dielectric hard mask on the metalhard mask.

FIG. 9 is a cross sectional view of the exemplary semiconductorstructure of FIG. 8 after patterning the dielectric hard mask and themetal hard mask.

FIG. 10 is a cross sectional view of the exemplary semiconductorstructure of FIG. 9 after patterning the conductive metal-containingmaterial to provide a conductive metal-containing structure utilizingthe patterned dielectric hard mask and the patterned metal hard mask asa combined etch mask, and removing the patterned dielectric hard maskand the patterned metal hard mask.

FIG. 11 is a cross sectional view of the exemplary semiconductorstructure of FIG. 10 after forming an optional spacer, a seconddielectric material layer, and a contact structure.

DETAILED DESCRIPTION

The present application will now be described in greater detail byreferring to the following discussion and drawings that accompany thepresent application. It is noted that the drawings of the presentapplication are provided for illustrative purposes only and, as such,the drawings are not drawn to scale. It is also noted that like andcorresponding elements are referred to by like reference numerals.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps and techniques, in order to provide an understanding ofthe various embodiments of the present application. However, it will beappreciated by one of ordinary skill in the art that the variousembodiments of the present application may be practiced without thesespecific details. In other instances, well-known structures orprocessing steps have not been described in detail in order to avoidobscuring the present application.

It will be understood that when an element as a layer, region orsubstrate is referred to as being “on” or “over” another element, it canbe directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “beneath” or “under” another element, it can bedirectly beneath or under the other element, or intervening elements maybe present. In contrast, when an element is referred to as being“directly beneath” or “directly under” another element, there are nointervening elements present.

Referring first to FIG. 1, there is illustrated an exemplarysemiconductor structure of the present application and during an earlystage of fabrication. The exemplary semiconductor structure shown inFIG. 1 includes a first interconnect dielectric material layer 12located on a substrate 10.

In some embodiments, the substrate 10 may include afront-end-of-the-line (FEOL) level. The FEOL level includes asemiconductor substrate having one or more semiconductor devices such,as, for example, transistors, capacitors, resistors, and etc. locatedthereon. In other embodiments, the substrate 10 may include one or moreinterconnect levels of a multilayered interconnect structure. In such anembodiment, each interconnect level would include one or moreelectrically conductive structures embedded in an interconnectdielectric material. A FEOL level is typically present beneath thelowest level of the multilayered interconnect structure.

The first dielectric material layer 12 may be composed of an inorganicdielectric material or an organic dielectric material. In someembodiments, the first dielectric material layer 12 may be porous. Inother embodiments, the first dielectric material layer 12 may benon-porous. Examples of suitable dielectric materials that may beemployed as the first dielectric material layer 12 include, but arelimited to, silicon dioxide, undoped or doped silicate glass,silsesquioxanes, C doped oxides (i.e., organosilicates) that includeatoms of Si, C, 0 and H, theremosetting polyarylene ethers or anymultilayered combination thereof. The term “polyarylene” is used in thispresent application to denote aryl moieties or inertly substituted arylmoieties which are linked together by bonds, fused rings, or inertlinking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide,or carbonyl.

In some embodiments, the first dielectric material layer 12 may have adielectric constant (all dielectric constants mentioned herein aremeasured relative to a vacuum, unless otherwise stated) that is about4.0 or less. In one example, the first dielectric material layer 12 canhave a dielectric constant of 2.8 or less. These dielectrics generallyhaving a lower parasitic cross talk as compared to dielectric materialswhose dielectric constant is greater than 4.0.

The first dielectric material layer 12 can be formed by a depositionprocess such as, for example, chemical vapor deposition (CVD), plasmaenhanced chemical vapor deposition (PECVD) or spin-on coating. The firstdielectric material layer 12 can have a thickness from 50 nm to 250 nm.Other thicknesses that are lesser than 50 nm, and greater than 250 nmcan also be employed in the present application.

Referring now to FIG. 2, there is illustrated the exemplarysemiconductor structure of FIG. 1 after forming an opening 14 into thefirst dielectric material layer 12. Although the present applicationdescribes and illustrates a single opening, the present application isnot limited to only forming a single opening 14 into the firstdielectric material layer 12. Instead, a plurality of openings can beformed into the first dielectric material layer 12.

In the present application, the opening 14 that is formed in the firstdielectric material layer 12 may be a via opening, a line opening or acombined via/line opening. The opening 14 may be formed by lithographyand etching. Lithography includes applying a photoresist material over amaterial or material stack to be patterned, exposing the photoresistmaterial to a pattern of irradiation, and developing the exposedphotoresist material. The etching may include an anisotropic etchetching process such as, for example, reactive ion etching. Inembodiments in which a combined via/line opening is formed, a seconditeration of lithography and etching may be used to form such anopening.

In some embodiments, and as is shown, the opening 14 extends through theentire depth of the first dielectric material layer 12. In otherembodiments (not shown), the opening 14 may extend partially through thefirst dielectric material layer. In yet further embodiments (and alsonot shown), and when multiple openings are formed, each opening may havea same depth, or the openings may have different depths.

Referring now to FIG. 3, there is illustrated the exemplarysemiconductor structure of FIG. 2 after forming an electricallyconductive structure 16 in the opening 14. In some embodiments (notshown), a diffusion barrier liner can be also be present in the opening14. In such an embodiment, the diffusion barrier liner separates theelectrically conductive structure 16 from the first dielectric materiallayer 12.

In some embodiments and when a diffusion barrier liner is formed, adiffusion barrier material is first formed into the opening 14 and on anexposed topmost surface of the first dielectric material layer 12. Thediffusion barrier material may include Ta, TaN, Ti, TiN, Ru, RuN, RuTa,RuTaN, W, WN or any other material that can serve as a barrier toprevent a conductive material from diffusing there through. Thethickness of the diffusion barrier material may vary depending on thedeposition process used as well as the material employed. In someembodiments, the diffusion barrier material may have a thickness from 2nm to 50 nm; although other thicknesses for the diffusion barriermaterial are contemplated and can be employed in the present applicationas long as the diffusion barrier material does not entirely fill theopening 14. The diffusion barrier material can be formed by a depositionprocess including, for example, chemical vapor deposition (CVD), plasmaenhanced chemical vapor deposition (PECVD), atomic layer deposition(ALD), physical vapor deposition (PVD), sputtering, chemical solutiondeposition or plating.

In some embodiments, an optional plating seed layer (not specificallyshown) can be formed in the opening as well. The optional plating seedlayer is employed to selectively promote subsequent electroplating of apre-selected conductive metal or metal alloy. The optional plating seedlayer may be composed of Cu, a Cu alloy, Jr, an Jr alloy, Ru, a Ru alloy(e.g., TaRu alloy) or any other suitable noble metal or noble metalalloy having a low metal-plating overpotential. Typically, Cu or a Cualloy plating seed layer is employed, when a Cu metal is to besubsequently formed within the at least one opening. The thickness ofthe optional plating seed layer may vary depending on the material ofthe optional plating seed layer as well as the technique used in formingthe same. Typically, the optional plating seed layer has a thicknessfrom 2 nm to 80 nm. The optional plating seed layer can be formed by aconventional deposition process including, for example, CVD, PECVD, ALD,or PVD.

An electrically conductive metal or metal alloy is formed into theopening 14; the electrically conductive metal or metal alloy providesthe electrically conductive structure 16 of the present application. Theelectrically conductive metal or metal alloy may be composed of copper(Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), nickel(Ni), iridium (Ir), rhodium (Rh) or an alloy thereof such as, forexample, a Cu—Al alloy. The electrically conductive metal or metal alloycan be formed utilizing a deposition process such as, for example, CVD,PECVD, sputtering, chemical solution deposition or plating. In oneembodiment, a bottom-up plating process is employed in forming theelectrically conductive metal or metal alloy. In some embodiments, theelectrically conductive metal or metal alloy is formed above the topmostsurface of the first dielectric material layer 12.

Following the deposition of the electrically conductive metal or metalalloy, a planarization process such as, for example, chemical mechanicalpolishing (CMP) and/or grinding, can be used to remove all portions ofthe electrically conductive metal or metal alloy (i.e., overburdenmaterial) that are present outside each of the openings forming theelectrically conductive structure 16. The planarization stops on atopmost surface of the first dielectric material layer 12. If present,the planarization process also removes the diffusion barrier materialfrom the topmost surface of the first dielectric material layer 12. Theremaining portion of the diffusion barrier material that is present inthe opening 14 is referred to herein as a diffusion barrier liner, whilethe remaining electrically conductive metal or metal alloy that ispresent in the opening 14 may be referred to as the electricallyconductive structure 16. Collectively, the first dielectric materiallayer 12, if present, the diffusion barrier liner, and the electricallyconductive structure 16 define a first level of the semiconductorstructure of the present application. This first level may be aninterconnect level or a middle-of-the-line (MOL) level.

Referring now to FIG. 4, there is illustrated the exemplarysemiconductor structure of FIG. 3 after forming, by selectivedeposition, a conductive landing pad 18 on a physically exposed surfaceof the electrically conductive structure 16. The conductive landing pad18 does not extend onto the topmost surface of the first dielectricmaterial layer 12. Instead, the conductive landing pad 18 is located onan entirety of the physically exposed surface of the electricallyconductive structure 16; a portion of the conductive landing pad 18 mayextend onto any diffusion barrier liner that is present in the opening14. As is illustrated in FIG. 4, the conductive landing pad 18 that isformed has a concave surface that is opposite a surface that forms aninterface with the physically exposed surface of the electricallyconductive structure 16.

The conductive landing pad 18 can be composed of cobalt (Co), ruthenium(Ru), tantalum (Ta), tungsten (W), titanium (Ti), rhodium (Rh), platinum(Pt), nickel (Ni) or any alloy or multilayered stack thereof. Theconductive landing pad 18 can have a thickness from 2 nm to 25 nm; otherthicknesses are possible and can be used in the present application asthe thickness of the conductive landing pad 18. The conductive landingpad 18 is formed utilizing a selective deposition such as, for example,CVD, PECVD, ALD or electroless deposition. The selective deposition ofthe conductive landing pad 18 may be performed at a depositiontemperature that is less than 500° C.

Referring now to FIGS. 5A-5B, there are illustrated the exemplarysemiconductor structure of FIG. 4 after performing a planarizationprocess such as, for example, chemical mechanical polishing (CMP).Notably, FIG. 5A illustrates the exemplary semiconductor structure ofFIG. 4 after performing a planarization process in which only arelatively small amount (e.g., from 0.5 nm to 3 nm) of an upper portionof the conductive landing pad 18 is subjected to CMP, while FIG. 5Billustrates the exemplary semiconductor structure of FIG. 4 afterperforming a planarization process in which a greater amount (e.g.,greater than 3 nm) of the upper portion of the conductive landing pad 18is subjected to CMP. In either embodiment, a planarized topmost surfaceis provided. In FIGS. 5A-5B, element 18P denotes a conductive landingpad structure that is formed after the planarization process. In someembodiments, the planarization step may be entirely omitted. In such anembodiment, the conductive landing pad 18 having the concave uppersurface may be used as the conductive landing pad structure.

The conductive landing pad structure 18P illustrated in FIG. 5A has acurved surface that connects the planar topmost surface of theconductive landing pad structure 18P to vertical sidewalls of theconductive landing pad structure 18P. The conductive landing padstructure 18P illustrated in FIG. 5B lacks such a curved surface and,instead, the planar topmost surface of the conductive landing padstructure 18P of FIG. 5B forms a right angle with each verticalsidewalls of the conductive landing pad structure 18P.

Referring now to FIG. 6, there is illustrated the exemplarysemiconductor structure of FIG. 5B after forming conductivemetal-containing material 20. As is shown, the conductivemetal-containing material 20 is a blanket layer that is formed onphysically exposed surfaces of the first dielectric material layer 12and physically exposed surfaces of the conductive landing pad structure18P. Although the structure shown in FIG. 5B is described andillustrated as being used, the present application contemplatesembodiments in which the conductive metal-containing material 20 isformed upon the structure shown in FIG. 4 or the structure shown in FIG.5A.

In some embodiments, the conductive metal-containing material 20 iscomposed of an electrically conductive metal or a metal alloy, asdefined above in providing the electrically conductive structure 16. Insuch an embodiment, the electrically conductive metal or metal alloythat provides conductive metal-containing material 20 may be the sameas, or different from, the electrically conductive metal or metal alloythat provides the electrically conductive structure 14. The electricallyconductive metal or metal alloy that provides the conductivemetal-containing material 20 may be formed utilizing one of thedeposition processes used to provide the electrically conductive metalor metal alloy layer that provides the electrically conductive structure16.

In other embodiments, the conductive metal-containing material 20 iscomposed of an electrically conductive metal-containing material stackwhich may be used as a non-volatile memory device such as, for example,a ferroelectric memory (FE) device, a resistive random access memory(ReRAM) device, a magnetoresistive random access memory (MRAM) device,or a phase change random access memory (PRAM) device.

A FE memory device is a random access memory similar in construction toa DRAM by using a ferroelectric layer instead of a dielectric layer toachieved non-volatility. FE memory devices typically include a materialstack of, from bottom to top, a bottom electrode, a ferroelectric layer,and a top electrode. The bottom and top electrodes may be composed of ametal or metal nitride. For example, TiN may be used as the material forboth the bottom and top electrodes. The ferroelectric layer is composedof one or more ferroelectric materials exhibiting ferroelectricity(i.e., a material that has a spontaneous electric polarization that canbe reversed by the application of an external electric field). Examplesof ferroelectric materials that can be used as the ferroelectric layerinclude, but at not limited to, mixed metal oxides such as, BaTiO₃,Pb(Zr_(x)Ti_(1-x)]O₃ (0.1≤x≤1), or crystalline HfO₂ with, or without, adoping element selected from Zr, Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si,Sr, Sn, C, N, and Y. The FE material stack can be formed by depositionof the various material layers.

A ReRAM device is a random access memory that typically includes amaterial stack of, from bottom to top, a bottom electrode, a metal oxidethat can exhibit a change in electron localization, and a top electrode.The bottom and top electrodes may be composed of a metal or metalnitride. For example, TiN may be used as the material for both thebottom and top electrodes. The metal oxide may include oxides of nickel,zirconium, hafnium, iron, or copper. The ReRAM material stack can beformed by deposition of the various material layers.

A MRAM device is a random access memory, that includes a magnetic tunneljunction (MTJ) structure. The magnetic tunnel junction (MTJ) structuremay include a magnetic reference layer, a tunnel barrier, and a magneticfree layer. The magnetic reference layer has a fixed magnetization. Themagnetic reference layer may be composed of a metal or metal alloy thatincludes one or more metals exhibiting high spin polarization. Inalternative embodiments, exemplary metals for the formation of themagnetic reference layer include iron, nickel, cobalt, chromium, boron,and manganese. Exemplary metal alloys may include the metals exemplifiedby the above. In another embodiment, the magnetic reference layer may bea multilayer arrangement having (1) a high spin polarization regionformed from of a metal and/or metal alloy using the metals mentionedabove, and (2) a region constructed of a material or materials thatexhibit strong perpendicular magnetic anisotropy (strong PMA). Exemplarymaterials with strong PMA that may be used include a metal such ascobalt, nickel, platinum, palladium, iridium, or ruthenium, and may bearranged as alternating layers. The strong PMA region may also includealloys that exhibit strong PMA, with exemplary alloys includingcobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum,cobalt-platinum, cobalt-palladium, iron-platinum, and/or iron-palladium.The alloys may be arranged as alternating layers. In one embodiment,combinations of these materials and regions may also be employed.

The tunnel barrier of the MTJ structure is composed of an insulatormaterial and is formed at such a thickness as to provide an appropriatetunneling resistance. Exemplary materials for the tunnel barrier includemagnesium oxide, aluminum oxide, and titanium oxide, or materials ofhigher electrical tunnel conductance, such as semiconductors orlow-bandgap insulators.

The magnetic free layer of the MTJ structure is composed of at least onemagnetic material with a magnetization that can be changed inorientation relative to the magnetization orientation of the referencelayer. Exemplary materials for the free layer of the MTJ structureinclude alloys and/or multilayers of cobalt, iron, alloys ofcobalt-iron, nickel, alloys of nickel-iron, and alloys ofcobalt-iron-boron. The MTJ structure of the MRAM device can be formed bydeposition of the various material layers.

A PRAM device is a random access memory that typically includes amaterial stack of, from bottom to top, a bottom electrode, a phasechange memory material that exhibits a change in atomic order (fromcrystalline to amorphous or vice versa), and a top electrode. The bottomand top electrodes may be composed of a metal or metal nitride. Forexample, TiN may be used as the material for both the bottom and topelectrodes. The phase change memory material may include a chalcogenideglass such as, for example, Ge₂Sb₂Te₅ or Ge₂Bi₂Te₆. The PRAM stack canbe formed by deposition of the various material layers.

Referring now to FIG. 7, there is illustrated of the exemplarysemiconductor structure of FIG. 6 after forming a metal hard mask 24 onthe conductive metal-containing material 20. In some embodiments, notshown, a planarization process may follow the formation of the metalhard mask 24.

The metal hard mask 24 may be composed of any metal-containing hard maskmaterial such as, for example, titanium nitride or tantalum nitride. Themetal hard mask 24 may be formed utilizing a deposition process such as,for example, CVD, PECVD, ALD, physical vapor deposition (PVD) orsputtering. The metal hard mask 24 may have a thickness from 20 nm to150 nm; although other thicknesses can also be used as the thickness ofthe metal hard mask 24.

Referring now to FIG. 8, there is illustrated the exemplarysemiconductor structure of FIG. 7 after forming a dielectric hard mask26 on the metal hard mask 24. The dielectric hard mask 26 may becomposed of any dielectric-containing hard mask material such as, forexample, silicon dioxide or silicon nitride. The dielectric hard mask 26may be formed utilizing a deposition process such as, for example, CVD,PECVD, ALD or PVD. The dielectric hard mask 26 may have a thickness from25 nm to 200 nm; although other thicknesses can also be used as thethickness of the dielectric hard mask 26.

Referring now to FIG. 9, there is illustrated the exemplarysemiconductor structure of FIG. 8 after patterning the dielectric hardmask 26 and the metal hard mask 24. The patterning of the dielectrichard mask 26 and the metal hard mask 24 can be achieved by lithography,as defined above, and etching. The etching may include an anisotropicetch etching process such as, for example, reactive ion etching. Theetching transfers a pattern provided by the patterned photoresist intothe hard mask stack of the dielectric hard mask 26 and the metal hardmask 24. The dielectric hard mask 26 that remains after this patterningstep may be referred to herein as a patterned dielectric hard mask 26P,while the metal hark mask 24 that remains after this patterning step maybe referred to herein as a patterned metal hard mask 24P. The etch stopson a surface of the conductive metal-containing material 20. Thepatterned photoresist can be removed after this patterning steputilizing a resist removal process such as, for example, stripping orashing.

The patterned dielectric hard mask 26P and the patterned metal hard mask24P are located over the conductive landing pad structure 18P and havesidewalls that vertically aligned to each other as well as beingvertically aligned to the underlying conductive landing pad structure18P that is sits on the electrically conductive structure 16.

Referring now to FIG. 10, there is illustrated the exemplarysemiconductor structure of FIG. 9 after patterning the conductivemetal-containing material 20 to provide a conductive metal-containingstructure 20P utilizing the patterned dielectric hard mask 26P and thepatterned metal hard mask 24P as a combined etch mask, and removing thepatterned dielectric hard mask 26P and the patterned metal hard mask24P. In some embodiments, the conductive metal-containing structure 20Pis another electrically conductive structure. In other embodiments, theconductive metal-containing structure 20P is a memory stack of a memorydevice as defined above.

During the patterning of the conductive metal-containing material 20,the physically exposed portions of the first dielectric material layer12 may be recessed as shown in FIG. 10. The recessed first dielectricmaterial layer is designated as element 12R in the drawings of thepresent application. The recessed first dielectric material layer 12Rhas a topmost surface that is located beneath a topmost surface of theelectrically conductive structure 16. As such, an upper portion of thesidewalls of the electrically conductive structure 16 is now physicallyexposed.

The patterning of the conductive metal-containing material 20 includesan anisotropic etching process such as, for example, ion beam etching,chemical wet etching or a combination of ion beam etching and chemicalwet etching. The etch removes portions of the conductivemetal-containing material 20 that are not located under the patterneddielectric hard mask 26P and the patterned metal hard mask 24P. Theremaining, i.e., non-etched, portion of the conductive metal-containingmaterial 20 that is located under the patterned dielectric hard mask 26Pand the patterned metal hard mask 24P constitutes the conductivemetal-containing structure 20P.

Since this etch does not remove any portion of the conductive landingpad structure 18P, no re-deposition of the conductive landing padmaterial (as conductive landing pad material particles) occurs on thesidewalls of the resultant conductive metal-containing structure 20P. Assuch the resultant structure does not exhibit any shorts that are causedby the re-deposition of the conductive landing pad material on asidewall of the conductive metal-containing structure.

The conductive metal-containing structure 20P has sidewalls that arevertically aligned to the sidewalls of the conductive landing padstructure 18P. In some embodiments, the sidewalls of the conductivemetal-containing structure 20 are also vertically aligned to thesidewalls of the electrically conductive structure 16.

After patterning of the conductive metal-containing material 20, thepatterned dielectric hard mask 26P and the patterned metal hard mask 24Pcan be removed utilizing one or more material removal processes. In oneexample, the patterned dielectric hard mask 26P and the patterned metalhard mask 24P can be removed utilizing a planarization process such as,for example, chemical mechanical polishing and/or grinding.

Referring now to FIG. 11, there is illustrated the exemplarysemiconductor structure of FIG. 10 after forming an optional spacer 28,a second dielectric material layer 30, and a contact structure 32. Thesecond dielectric material layer 30 defines an upper level of thestructure of the present application.

When present, the spacer 28 is composed of a dielectric spacer materialsuch as, for example, silicon dioxide, silicon nitride or a low-kmaterial having a dielectric constant of less than the 4.0. The spacer28 may be formed by deposition of the dielectric spacer material andthereafter subjecting the deposited dielectric spacer material to aspacer etch.

In some embodiments, and as shown, the spacer 28 has a base that islocated on a physically exposed portion of the recessed first dielectricmaterial layer 12R and has a sidewall that is present along thephysically exposed upper portion of the sidewalls of the electricallyconductive structure 16, the entirety of the sidewalls of the conductivelanding pad structure 18P and a lower portion of the sidewalls of theconductive metal-containing structure 20P.

The second dielectric material layer 30 is formed laterally surroundingthe entirety of the conductive landing pad structure 18P and an entiretyof the conductive metal-containing structure 20P, and is present above atopmost surface of the conductive metal-containing structure 20P. Insome embodiments and when the first dielectric material layer 12 isrecessed, the second dielectric material layer 30 laterally surrounds anupper portion of the electrically conductive structure 16 as well. Thesecond dielectric material layer 30 has a surface that directly contactsphysically exposed portions of first dielectric material layer 12 oralternatively, the recessed first dielectric material layer 12R.

The second dielectric material layer 30 may include one of thedielectric materials mentioned above for the first dielectric materiallayer 12. In some embodiments, the second dielectric material layer 30is composed of a same dielectric material as the first dielectricmaterial layer 12. In other embodiments, the second dielectric materiallayer 30 is composed of a dielectric material that is compositionallydifferent from the dielectric material that provides the firstdielectric material layer 12. The second dielectric material layer 30may be formed utilizing one of the deposition processes mentioned abovein forming the first dielectric material layer 12. The second dielectricmaterial layer 30 has a thickness that can be in the thickness rangementioned above for the first dielectric material layer 12.

Contact structure 32 is then formed into the second dielectric materiallayer 30. The contact structure 32 has at least one surface thatcontacts at least one surface of the conductive metal-containingstructure 20P. In some embodiments, the contact structure 32 is indirect physical contact with a topmost surface of the conductivemetal-containing structure 20P. In other embodiments, the contactstructure 32 is in direct physical contact with an upper portion of thesidewalls of the conductive metal-containing structure 20P and a topmostsurface of the conductive metal-containing structure 20P.

The contact structure 32 may be composed of one of the electricallyconductive metals or metal alloys mentioned above for providing theelectrically conductive structure 16. In one embodiment, the contactstructure 32 is composed of a same electrically conductive metal ormetal alloy as the electrically conductive structure 16. In otherembodiment, the contact structure 32 is composed of an electricallyconductive metal or metal alloy that is compositionally different fromthe electrically metal or metal alloy that provides the electricallyconductive structure 16. The contact structure 32 can be formed by firstproviding a contact opening in the second dielectric material layer 30.The contact opening can be formed by lithography and etching. Anoptional diffusion barrier material, as defined above, can be formedinto the contact opening prior to filling of the contact opening with anelectrically conductive metal or metal alloy. The filling of the contactopening with the electrically conductive metal or metal alloy mayinclude one of the deposition processes mentioned above for forming theelectrically conductive metal or metal alloy that provides theelectrically conductive structure 16. A planarization process may followthe filling of the contact opening with the electrically conductivemetal or metal alloy. The contact structure 32 has a topmost surfacethat is coplanar with a topmost surface of the second dielectricmaterial layer 30.

FIG. 11 illustrates an exemplary semiconductor structure of the presentapplication. Notably, FIG. 11 illustrates a semiconductor structure thatincludes an electrically conductive structure 16 embedded in a firstdielectric material layer 12 (or 12R). A conductive landing padstructure 18P is located on an entirety of a surface of the electricallyconductive structure 16, a conductive metal-containing structure 20P islocated on an entirety of a surface of the conductive landing padstructure 18P, and a contact structure 32 physically contacts at leastone surface of the conductive metal-containing structure 20P. Inaccordance with the present application, the conductive landing padstructure 18P, the conductive metal-containing structure 20P, and thecontact structure 32 are embedded in a second dielectric material layer30 that is present above the first dielectric material layer 12 (or12R), and the conductive metal-containing structure 20P has sidewallsthat are devoid of re-deposited conductive landing pad materialparticles.

As is further illustrated, the sidewalls of the conductivemetal-containing structure 20P are vertically aligned to the sidewallsof the conductive landing pad structure 18P. Also, and in theillustrated embodiment, the sidewalls of the conductive metal-containingstructure 20P are vertically aligned to the sidewalls of theelectrically conductive structure 16. In some embodiments, the exemplarystructure shown in FIG. 11 is an interconnect structure. In otherembodiments, the exemplary structure of FIG. 11 is a memory device.

While the present application has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present application. It is therefore intended that the presentapplication not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

What is claimed is:
 1. A semiconductor structure comprising: an electrically conductive structure embedded in a first dielectric material layer; a conductive landing pad structure located on an entirety of a surface of the electrically conductive structure; a conductive metal-containing structure located on an entirety of a surface of the conductive landing pad structure; and a contact structure contacting at least one surface of the conductive metal-containing structure, wherein the conductive landing pad structure, the conductive metal-containing structure, and the contact structure are embedded in a second dielectric material layer that is present above the first dielectric material layer, and wherein the conductive metal-containing structure has a sidewall devoid of re-deposited conductive landing pad material particles.
 2. The semiconductor structure of claim 1, wherein the sidewall of the conductive metal-containing structure is vertically aligned to a sidewall of the conductive landing pad structure.
 3. The semiconductor structure of claim 2, wherein the first dielectric material layer has a recessed surface compared to a topmost surface of the conductive landing pad structure.
 4. The semiconductor structure of claim 3, further comprising a spacer located on sidewalls of the electrically conductive structure, the conductive landing pad structure and the conductive metal-containing structure.
 5. The semiconductor structure of claim 1, wherein the conductive metal-containing structure is composed of an electrically conductive metal or metal alloy.
 6. The semiconductor structure of claim 1, wherein the metal-containing structure is composed of a non-volatile memory stack.
 7. The semiconductor structure of claim 6, wherein the non-volatile memory stack includes a ferroelectric (FE) memory stack, a resistive random access memory (ReRAM) stack, a magnetoresistive random access memory (MRAM) stack, or a phase change random access memory (PRAM) stack.
 8. The semiconductor structure of claim 1, wherein the least one surface of the conductive metal-containing structure is a topmost surface.
 9. The semiconductor structure of claim 1, wherein the least one surface of the conductive metal-containing structure is a topmost surface and a sidewall surface.
 10. The semiconductor structure of claim 1, wherein the contact structure has a topmost surface that is coplanar with a topmost surface of the second dielectric material layer.
 11. The semiconductor structure of claim 1, further comprising a substrate located beneath the first dielectric material layer, wherein the substrate comprises a front-end-of-the-line level.
 12. The semiconductor structure of claim 1, further comprising a spacer located along an upper portion of a sidewall of the electrically conductive structure, an entirety of a sidewall of the conductive landing pad structure, and only a lower portion of the sidewall of the conductive metal-containing structure.
 13. The semiconductor structure of claim 12, wherein a portion of the contact structure directly contacts an upper portion of the sidewall of the conductive metal-containing structure.
 14. The semiconductor structure of claim 13, wherein the spacer has a bottommost surface contacting a topmost surface of the first dielectric material layer.
 15. The semiconductor structure of claim 12, wherein the spacer has a bottom width that is greater than a top width.
 16. The semiconductor structure of claim 1, wherein the contact structure has a width greater than a width of each of the metal-containing structure, the conductive landing pad structure, and the electrically conductive structure.
 17. A semiconductor structure comprising: an electrically conductive structure embedded in a first dielectric material layer; a conductive landing pad structure located on an entirety of a surface of the electrically conductive structure; a magnetic tunnel junction structure located on an entirety of a surface of the conductive landing pad structure; and a contact structure contacting at least one surface of the magnetic tunnel junction structure, wherein the conductive landing pad structure, the magnetic tunnel junction structure, and the contact structure are embedded in a second dielectric material layer that is present above the first dielectric material layer, and wherein the magnetic tunnel junction structure has a sidewall devoid of re-deposited conductive landing pad material particles.
 18. The semiconductor structure of claim 17, further comprising a spacer located along an upper portion of a sidewall of the electrically conductive structure, an entirety of a sidewall of the conductive landing pad structure, and only a lower portion of the sidewall of the magnetic tunnel junction structure.
 19. The semiconductor structure of claim 18, wherein a portion of the contact structure directly contacts an upper portion of the sidewall of the magnetic tunnel junction structure.
 20. The semiconductor structure of claim 18, wherein the spacer has a bottommost surface contacting a topmost surface of the first dielectric material layer. 